JFET Buffer and buffer cable

[JohnH]

Something is not quite right!

Try picking through this:

Check point: The order of the leads top to bottom on a schematic diagram is positive battery=drain, gate, source, then through 22k to ground. The physical placement of the three leads on the actual jfet is a different order, source is in the middle. So please check its the right way around and connected rightly.

Back to the circuit:

The biasing resistors are a voltage divider. They feed to the gate of the jfet, which is one of its outer leads.(check on the diagram I linked). The gate of the jfet is very high impedance, so the dc voltage at the gate is determined by the resistors. eg, let's say you have a 3.3M resistor to positive and a 2.2M to ground, with a 9V battery: The voltage at the gate (previously we were measuring at the source) should be:

9V x 2.2/(2.2+3.3) = 3.6V

Try this calc with your values and compare to measurements.

Still measuring at the gate, if you pull out the jfet this voltage should not change significantly.

Now returning to measuring at the source as before:

On the circuit, when correctly running, the source voltage (which is where the output is taken from) should be higher than that of the gate. This is where jfets differ even in the same batch. I found that this source-to-gate voltage difference can be between about 1 5V to 2.5V with the 2N5457's that I have.

So if gate was 3.6V, source would be 5.1V to 6 1V with a 9V battery Which is an OK range.

Your values seem to be lower than they should be, almost like they are gate voltages not source voltages?

Now to using it with a 6V supply:

Let's say you use 3.3M and 1.2M. we expect at the gate:
6V x 1 2 / (1.2 + 3 3) = 1.6V

At the source, add 1.5 to 2.5V to get 3.1V to 4.1V

Does any of that reveal anything?

[roadtonever]

With 2.2+3.3M my gate reads 1.6v, pulling out the JFET it stays at 1.6v. I get a 3.7v when measuring source.

With 6v power my gate reads 1.1v(pulling out JFET stays at 1.1v). Source reads 2.7v.


Am I doing something wrong with my breadboard layout? Basically I copied the stripboard layout using battery negative as ground. This is probably where I screwed up but IDK how to fix it. Also checked my resistors with two meters.




The circuit is functional when I plug it into my audio interface(disconnecting 9v kills audio). (Is it just me or is it brighter at 9V vs 6v?)



Probably not an out of spec or fake JFET. However the store I ordered the 2N5457 from had a customer comment about the source and drain pins behaving the same in his circuit when he reversed "all eight of them". Is this weird or normal? Otherwise the store lists the same pinout.


I also have a J113 JFET on hand. If it's useful for troubleshooting, the drain voltage is 1.6v and the source is 5.1v with 2.2+3.3M & 9v.

[JohnH]

Seems like the jfet is working! It's odd you get 1.6V At the gate with a 9V supply and 3.3M and 2.2M resistors. Can you check the resistors by measuring them?

[roadtonever]

2.19k, 2.36M & 3.249M.

[JohnH]

The source voltages look to be a credible amount more than the gate voltages. And it seems that your circuit is basically working? But I cant figure out why your gate voltages are so low. Its really basic electronics 101, and with a 6V supply, and 2.2M to ground, 3.3M to positive, the gate voltage should be 2.2/5.5 x 6 = 2.4V.

Maybe check the power voltage with the circuit running? ie ground to drain (the jfet lead that goes to +ve.)

Also, was that reading 2.19k as noted? or 22k (as intended) ?

[MattB]

Mar 19, 2014 14:31:37 GMT -5 JohnH said:

I recently built a version of this buffer. The 2N5457s I bought on Aliexpress turned out to be fake, so I used a J113 instead. So this post is just to share what data I have on J113s in case somebody else might find it useful.

The datasheet values given for the J113 are Vgs(off) between -0.5V and -3.0V and a minimum Idss of 2mA. The value given for Idss is a little misleading, because typical values are much higher than the minimum.

Here are the Vgs(off)/Idss values I measured for 10 Onsemi brand J113s:

-1.69V/17.2mA

-1.70V/17.8mA

-1.71V/17.7mA

-1.72V/18.0mA

-1.74V/18.1mA

-1.75V/18.5mA

-1.80V/19.2mA

-1.81V/19.0mA

-1.82V/19.4mA

-1.89V/20.3mA

Average: -1.76V/18.5mA

And here are two charts from the datasheet, which show typical values for Id vs Vgs for a range of Vgs(off) values. Idss could be anywhere from 7mA to almost 40mA, so even the lowest typical values are well above the datasheet minimum.

For Vgs(off)=-1.6V the Idss shown is around 16mA. For Vgs(off)=-2.0V the Idss shown is a little over 20mA.

My ten sets of values all sit within the range bounded by those two pairs, so my measurements are a fairly good match to these charts.

I wanted to see how much difference the variation in Vgs(off) and Idss made in practice, so I breadboarded the above circuit and picked three J113s to measure that covered the range of values I have. Here are the Vgs(off) and Idss for the 3 JFETs I used:

#1: 1.69V/17.2mA

#2: 1.75V/18.5mA

#3: 1.89V/20.3mA

With the breadboard circuit exactly as in JohnH's diagram, I measured the following values for source voltage and current draw:

JFET #1: 5.95V/271µA

JFET #2: 6.01V/274µA

JFET #3: 6.15V/281µA

With R12 increased from 2.2M to 3.3M, and everything else the same I measured the following values for source voltage and current draw:

JFET #1: 5.18V/236µA

JFET #2: 5.23V/239µA

JFET #3: 5.36V/245µA

I tried importing and editing the Onsemi J113 model in LTSpice to match JFET #2, and I got results that were very close to the real world measurements; source voltage within 0.1V and current within 5µA for both versions of the breadboard circuit. The reason I wanted to do this is so I could run a transient and fourier analysis and see how much headroom I had available, and what the performance was like at low battery levels.

With R12 set to 2.2M and a 9V supply, and with the buffer output connected to a 20k load, the circuit can handle an input level of over 5V peak-to-peak with less than 0.5% THD.

At 4.8V supply, that drops to just under 1.4V peak-to-peak at 0.5% THD.

With R12 set to 3.3M, headroom at 9V supply is around 4.2V peak-to-peak at 0.5% THD.

At 4.8V supply, headroom is around 2.4V peak-to-peak at 0.5% THD.

With R12 at 3.3M, current draw is lower and headroom at low supply voltage is higher, so that's the version I used. 

I put the buffer in a HSH strat copy and it sounds very good- clean and clear with no colouration that I could hear. I added 220pF and 470pF caps on DIP switches, and I found that the single coil and split selections sounded good with 470pF, or even 790pF of added capacitance, but I liked the sound of the humbuckers better with just 220pF added. I think it's very much worth experimenting with a few different cap values and seeing which you like best.

[JohnH]

Thanks for posting that, which all makes good sense. I used to breadboard these with the specific jfets that I was going to use, to pick the best bias resistors since the jfets are pretty inconsistent.

Another aspect of the circuit that you posted is that the output parts are sized to give it ability to drive a line-in connection, which have much lower impedance than a guitar amp input. For this, I thought it better to set the source voltage a bit higher, which helps the jfet pull the signal both down and up with the best overall headroom before clipping.

I'm glad it works and sounds good!

[roadtonever]

JohnH

I want to revisit this and now considering active mixing the coils of the single MM style humbucker pictured in Reply #151

Specifically I want a parallel config that is free from mutual load between the coils, like some EMGs internally. Basically split characteristics as far as DCR and resonant peak goes except with both coils sensing the strings.


Can your board layout be adapted for this goal by changing values and/or using two boards? If so do you want to make a simple drawing when you have the time? I'll gladly test it on the breadboard and in the bass in that case.

Stock controls are like a passive jazz bass(4-conductor pickup leads). I don't mind making some changes to the controls if it makes it adapting your layout easier. But I prefer to keep the single output jack and add a single 9v battery.

[JohnH]

This version might work for what you want:

guitarnuts2.proboards.com/thread/4595/active-pickup-blender-volume-module

It uses the jfet buffer and adds a blend pot at the front end to pan between two pickups, without mutual loading (except via a 500k pot). You could add a master volume after that, eg 100k.